The present invention relates to a delay locked loop circuit. The delay locked loop circuit (DLL) is used for detecting an optimum strobe point of a clock signal for a data signal during a memory access, or the like. For example, in the case of single data rate (SDR), the delay locked loop circuit detects a ½ phase of a reference clock signal, whereas in the case of double data rate (DDR), the delay locked loop circuit detects a ¼ phase or ¾ phase of the reference clock signal. In general, in a memory, or the like, the delay locked loop circuit is used for timing sequence control of a word line, a sense amplifier, or the like.
FIG. 16 shows a structure of a conventional delay locked loop circuit. A delay circuit 100 includes four delay elements 101 which are connected in series. The delay circuit 100 delays reference clock signal CLKr by one cycle to output delayed clock signal CLKd. A phase comparator 102 compares the phases of reference clock signal CLKr and delayed clock signal CLKd to output signal UP and signal DN according to the comparison result. A charge pump circuit 103 (including a loop filter) controls the delay circuit 100 based on signal UP and signal DN. The delay locked loop circuit having such a structure becomes stable when the phase of delayed clock signal CLKd is delayed from the phase of reference clock signal CLKr by one cycle, and at this point in time, the delay of delayed clock signal CLKd is locked.
In the delay locked loop circuit having the above structure, the delay element 101 at the first stage of the delay circuit 100 outputs a clock signal delayed by a ¼ phase (90°). The delay element 101 at the third stage of the delay circuit 100 outputs a clock signal delayed by a ¾ phase (270°).
In the conventional delay locked loop circuit, the driving capacity and load capacity are different between reference clock signal CLKr and the delay element 101. Therefore, it is difficult to improve the accuracy for ¼ phase and ¾ phase.
In the conventional delay locked loop circuit, the delayed clock signal is generated to have a delay of ¼ phase or ¾ phase from the reference clock signal irrespective of the duty ratio of the reference clock signal. Thus, for example, if the duty ratio of the reference clock signal is lower than 25%, the ¼ phase-delayed clock signal does not rise or fall during an on-duty period of the reference clock signal, and therefore, the conventional delay locked loop circuit cannot be used with DDR. That is, there is a possibility that the conventional delay locked loop circuit does not normally operate with a reference clock signal whose duty ratio is not 50%.
In the conventional delay locked loop circuit, based on its principle, signals UP and DN having extremely short pulses are output even after the delay of delayed clock signal CLKd is locked. Therefore, the conventional delay locked loop circuit has static jitters. Although the static jitters can be suppressed by decreasing a delay gain, the decrease of the delay gain deteriorates the response speed achieved till the delay is locked, i.e., delays the locking time. Alternatively, the static jitters can be suppressed by increasing the capacitance of a loop filter to have a larger filter time constant. However, in this case, the circuit scale increases.